1. Field
Example embodiments relate to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a flash memory device and a method of manufacturing the same.
2. Description of the Related Art
In general, non-volatile memory devices (e.g., flash memory devices) can maintain data stored therein even when the power is shut off, and thus the non-volatile memory devices have been widely used for data storage devices. For example, the non-volatile memory devices may have been used as a ROMBIOS for a personal computer, a storage memory for a setup box, a server system for a printer system and various network systems. Recently, the non-volatile memory devices may have been used as a memory system for a digital camera and a mobile phone.
The flash memory device can electrically store (program) or erase data by the unit of a sector of memory cells by increasing or decreasing the threshold voltage of cell transistors of the memory cells. Hot electrons may be generated at the drain electrode of the cell transistor and accumulate in the floating gate through the channel of the cell transistor, increasing the threshold voltage of the gate electrode of the cell transistor. The data is programmed in the memory cell of the flash memory device as a binary code of ‘1’. In contrast, when a high voltage is applied between the source electrode and the floating gate of the cell transistor, the accumulated hot electrons are discharged from the floating gate to the substrate through the channel, decreasing the threshold voltage of the gate electrode. Therefore, the data is erased from the cell transistor of the flash memory device and the memory cell is allocated as a binary code of ‘0’.
A cell transistor of the flash memory cell generally includes a stack gate structure, and source and drain regions at both sides of the stack gate structure on an active region of a semiconductor substrate. A tunnel oxide layer, a floating gate, a dielectric layer and a control gate are sequentially stacked on the active region of the substrate to form the stack gate structure, and the source/drain regions may be arranged at surface portions of the active region of the substrate adjacent to the stack gate structure. A channel is positioned under the stack gate structure. The source and drain regions may be spaced apart by the channel region.
Conventionally, the stack gate structure is formed on the substrate by consecutive first and second etching processes. A floating gate pattern is formed on the substrate along a direction of a bit line of the flash memory device by the first etching process. Then, the floating gate pattern process is node-separated into a plurality of floating gates at each cell, and a control gate line is formed on the floating gates along a direction of the word line of the flash memory device by the second etching process.
Particularly, the floating gate pattern is formed into a line shape along a first direction on a tunnel insulation layer of the substrate by the first etching process. Then, the dielectric layer is formed on the floating gate pattern to cover the floating gate pattern and a device isolation layer, and a control gate layer is formed on the dielectric layer. The control gate layer, the dielectric layer and the floating gate pattern are sequentially etched off as a line shape along a second direction perpendicular to the first direction by the second etch process, to thereby form the control gate line, a dielectric pattern under the control gate pattern and the node-separated floating pattern under the dielectric pattern. The active regions at both sides of the node-separated floating gate pattern are exposed and self-aligned with the floating gate pattern in the second etching process. The active regions exposed at both sides of the floating gate pattern are provided as source/drain regions of the memory devices. A cell transistor is formed on the substrate including the stack gate structure in which the floating gate pattern, the dielectric pattern and the control gate pattern are stacked on the tunnel insulation layer and the source/drain electrodes at both sides of the stack gate structure.
When the second etching process is excessively performed in a direction of the bit line of the memory device, the control gate line and the floating gate pattern are over etched, and thus widths of the control gate line and the floating gate pattern are significantly reduced along the bit line direction. Accordingly, a number of charge trap sites are generated on the dielectric pattern between the control gate line and the floating gate pattern, which deteriorates the data retention characteristics of the flash memory device.
FIG. 1 is a perspective view illustrating a structure of a conventional flash memory device.
As illustrated in FIG. 1, side surfaces of the control gate line 50 and the floating gate pattern 30 are usually over-etched in the second etching process along the bit line direction which is in parallel with a direction of the line-shaped active region A of the substrate 10, and thus first and second uncovered areas U1 and U2 are usually provided with the conventional flash memory device. Some of the tunnel insulation layer and the dielectric pattern are not covered with the floating gate pattern 30, and thus a top surface of the tunnel insulation layer and a lower surface of the dielectric pattern are partially exposed to the first uncovered area U1. In the same way, some of the dielectric pattern is not covered with the control gate line 50, and thus an upper surface of the dielectric pattern is partially exposed to the second uncovered area U2.
When an ion implantation process is performed onto surface portions of the active region A of the substrate 10 at both sides of the stack gate structure, ion charges are usually implanted onto the uncovered dielectric pattern 40, as well as the source/drain regions, to thereby form the charge trap sites on the dielectric pattern 40.
When the stack gate structure including the charge trap sites is used as a cell transistor or a selection transistor of the flash memory device, the charges captured by the floating gate pattern tend to travel into the charge trap sites of the dielectric pattern 40 by thermal energy of a room temperature. Therefore, the binary data at the cell transistor may be unexpectedly erased and the data retention characteristics of the flash memory device are substantially deteriorated.
Accordingly, there is still a need for a flash memory device in which the dielectric pattern is sufficiently covered, and thus no charge trap sites are provided on the dielectric pattern, to thereby increase the data retention characteristics of the flash memory device.